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instruction queue

См. также в других словарях:

  • Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… …   Wikipedia

  • Double-ended queue — Not to be confused with Double ended priority queue. In computer science, a double ended queue (dequeue, often abbreviated to deque, pronounced deck) is an abstract data structure that implements a queue for which elements can only be added to or …   Wikipedia

  • Prefetch input queue — Most modern processors load their instructions some clock cycles before they execute them. This is achieved by pre loading machine code from memory into a prefetch input queue (PIQ).This behavior only applies to von Neumann computers (that is,… …   Wikipedia

  • Out-of-order execution — In computer engineering, out of order execution (OoOE or OOE) is a paradigm used in most high performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay. In this paradigm, a… …   Wikipedia

  • Intel 8086 — Produced From 1978 to 1990s Common manufacturer(s) Intel, AMD, NEC, Fujitsu, Harris (Intersil), OKI, Siemens AG …   Wikipedia

  • Tomasulo algorithm — The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo from IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to execute non sequentially (out of order execution). It… …   Wikipedia

  • AMD K10 — AMD K10 (auch bekannt als „AMD Next Generation Processor Technology“ oder „Stars“) ist der Codename einer Generation von Mikroprozessoren von AMD, die die K8 und K9 Generation ergänzt und mittelfristig ersetzen wird. Die K10 Generation… …   Deutsch Wikipedia

  • Memory disambiguation — is a set of techniques employed by high performance out of order execution microprocessors that execute memory access instructions (loads and stores) out of program order. The mechanisms for performing memory disambiguation, implemented using… …   Wikipedia

  • Register renaming — In computer engineering, register renaming refers to a technique usedto avoid unnecessary serialization of program operations imposed by the reuseof registers by those operations.Problem definitionPrograms are composed of instructions which… …   Wikipedia

  • Classic RISC pipeline — In the history of computer hardware, some early reduced instruction set computer central processing units (RISC CPUs) used a very similar architectural solution, now called a classic RISC pipeline. Those CPUs were: MIPS, SPARC, Motorola 88000,… …   Wikipedia

  • TRIPS-Prozessor — Gehäuse des TRIPS Prozessors Der TRIPS Prozessor (Tera op, Reliable, Intelligently adaptive Processing System) ist ein Forschungsprozessor der University of Texas at Austin. Die Prozessorarchitektur ist so ausgelegt, dass sich weitere Kerne… …   Deutsch Wikipedia

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